In the design of semiconductor devices such as high-frequency integrated circuits, it is sometimes desirable that only the intrinsic characteristics of a semiconductor device be incorporated in the design process. The intrinsic characteristics can be determined by characterizing a test device. However, determination of the intrinsic characteristics can be problematic due to unwanted parasitics in the characterization process resulting from the process of fabricating the associated test devices. De-embedding is a process that is utilized to remove the effects of the parasitics from the characteristics of the device under test.
FIGS. 1-6 are functional schematics of 2-port test structures typically used in prior art de-embedding processes. FIG. 1 is a schematic representation of test structure 101 that includes a transmission-configured two terminal device under test (DUT) 111, shown as a two-port network. Examples of such devices include capacitors, diodes, inductors, resistors, or any other two terminal devices. In one embodiment, DUT 111 is fabricated on a substrate of a semiconductor wafer with input port 103 and output port 107 located on the wafer surface for radio frequency (rf) characterization.
FIG. 2 is a schematic representation of a “through” test structure 201 typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 201 have the same electrical length and port characteristics as test structure 101 exclusive of DUT 111.
FIG. 3 is a schematic representation of a “short” test structure 301 typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 301 have the same port characteristics and the same electrical length as test structure 101, but with rf “shorts” at locations corresponding to the locations of the input and output ports of DUT 111.
FIG. 4 is a schematic representation of an “open” test structure 401 typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 401 have the same port characteristics and the same electrical length as test structure 101, but with rf “opens” at locations corresponding to the locations of port-1 and port-2 the input and output ports of DUT 111.
FIG. 5 is a schematic representation of a “left” test structure 501 typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 501 have the same port characteristics and the same electrical length as test structure 101, but with an rf “match” at the location corresponding to the location of the input port 103 and an rf “open” at the location corresponding to the location of the output port 107 of DUT 111.
FIG. 6 is a schematic representation of a “right” test structure 601 typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 601 have the same port characteristics and the same electrical length as test structure 101, but with an rf “match” at the location corresponding to the location of the output port 107 and an rf “open” at the location corresponding to the location of the input port 103 of DUT 111.
Test structures 201, 301, 401, 501, and 601 (test structures 201-601) are constructed from the same fabrication process as test structure 101 of FIG. 1.
A variety of methods can be used with the test structures 201-601 to determine the intrinsic characteristics of DUT 111, such as the open-short method, three-step method, and four-port method. However, these methods individually may not de-embed the DUT 111, particularly for very high frequency semiconductor devices within desired parameters. Accordingly, a new process of de-embedding would be useful.